1. Field of the Invention
The present invention relates to a semiconductor device and manufacturing method thereof and, more specifically, to a semiconductor device having a trench isolation structure and a method of manufacturing the same.
2. Description of the Background Art
In a semiconductor device having an integrated circuit that must withstand a high voltage, an isolation structure for electrically separating elements from each other is necessary, in order to avoid electrical influence between elements. Particularly, trench isolation has been known as a superior method of element isolation to attain higher degree of integration, as it requires relatively small area for separating elements. An isolation structure having a combination of an SOI (Silicon On Insulator) substrate and the trench isolation has been highly appreciated as one element can fully be isolated from another element electrically so that parasitic operation between elements can be suppressed.
An example of a semiconductor device using such an SOI substrate will be described. An N− layer is formed on a silicon semiconductor substrate with a BOX (Buried OXide Layer) layer interposed. In the N− layer, an element forming region is formed, and a trench isolation region is formed for separating elements. In the element forming region, an n channel type MOS (Metal Oxide Semiconductor) transistor including a source, drain, gate and a body is formed as a semiconductor element.
In semiconductor devices described in Japanese Patent Laying-Open Nos. 2001-044437 and 2003-197639, semiconductor devices having a P type region formed to be in contact with the trench isolation region are proposed. The conventional semiconductor devices using an SOI substrate are structured as described above.
In the conventional semiconductor device, the N− layer in the element forming region is in contact with the trench isolation region, and therefore, when the MOS transistor is off, an electric field reaches the trench isolation region. Therefore, in order to prevent decrease in main breakdown voltage of the MOS transistor caused by electric field concentration near the trench isolation region, it has been necessary to ensure a sufficient distance between the P type impurity region as the body of the MOS transistor formed in the element forming region and the trench isolation region. As a result, the element forming region comes to occupy a large area.
When the MOS transistor is off, the electric field reaches even the inside of the trench isolation region, possibly eroding reliability over a long period dependent on the material of the trench isolation region.
Further, in some state of operation of the MOS transistor, a P type inverted layer may be formed on an upper surface of the BOX layer. At this time, as the P type impurity region formed on the surface of the N− layer is not in contact with the BOX layer, formation of the inverted layer delays in a high speed operation, undesirably decreasing the switching speed.
In the semiconductor devices described in Japanese Patent Laying-Open Nos. 2001-044437 and 2003-197639, the P type region formed to be in contact with the trench isolation region is connected to two or more different electrode terminals. Therefore, it is impossible to control the electric field in the element forming region, and therefore, there has been a limit in improving the performance of trench isolation.